1. Technical Field
The present invention generally relates to semiconductor wafer manufacture in the presence of particle contamination, and more particularly to the field of in-line defect disposition and yield forecasting in a real-time semiconductor wafer manufacturing environment.
2. Background of the Related Art
Currently, various wafer inspection and failure analysis tools are available which provide detailed qualitative and quantitative information regarding failures and processing defects which are experienced by semiconductor wafers and devices embedded therein. The qualitative and quantitative information is typically isolated or segregated in accordance with a specific inspection and analysis tool. Efforts have been made to display the outputs of the different wafer analysis tools together so that engineers can view the results of the different analysis tools to analyze the various defects encountered by a semiconductor wafer.
The problem of displaying various information output from different wafer analysis tools is exacerbated by the fact that most wafer analysis tools collect, process, and store data in a proprietary fashion. Accordingly, data can not be easily retrieved and displayed together. As a result, engineers are generally forced to use one wafer inspection and analysis tool at a time. The engineer must then transfer the semiconductor wafer from inspection tool to inspection tool.
For example, in-line defect measurement instruments have been used to count the total number of external particles introduced into the semiconductor wafer as a result of the inherent fallibilities of the manufacturing process. If one semiconductor wafer is discovered to have experienced contamination by more particles than other semiconductor wafers, the semiconductor wafer with the highest particle count will typically be assigned the highest priority for defect analysis and disposition. FIGS. 1-2 illustrate such a situation where semiconductor wafer 2 contains five particles 4, and semiconductor wafer 2' contains eleven particles 4'. Under this scenario, semiconductor wafer 2' would be given a higher priority with respect to defect analysis and disposition than semiconductor wafer 2.
Hence, based on the above, one step in the manufacture of a semiconductor wafer includes inspection and analysis to determine the origination of causes of defects in accordance with the number of particles discovered on the semiconductor wafer. However, not all particles introduced into the semiconductor devices will cause defects. Therefore, analyzing semiconductor wafers with more particles thereon may not produce dramatic increases in device yield. It also tends to overestimate particle-caused yield loss. Thus, much labor may be unnecessarily expended without any substantial increase in device yield.
For example, FIGS. 3-4 illustrate a second method of analyzing a semiconductor wafer to determine whether to inspect and analyze it for defects. As shown in FIG. 3, a schematic illustration of a portion of a semiconductor device in a semiconductor wafer, circuit conductor lines 6 and 8 are designed in the semiconductor wafer to conduct electrical signals independently of one another. Due to imperfections in the semiconductor wafer manufacturing process, particle 10 has been introduced between conductors 6 and 8. Particle 10 does not interfere with either of conductors 6 and 8 and will generally not affect the functionality (or yield) of the semiconductor device or wafer. Accordingly, even though particle 10 is a result of a defect in the semiconductor wafer manufacturing process, the particle does not cause failure in the semiconductor device by disturbing signals flowing in conductors 6 and 8.
FIG. 4 is also a schematic illustration of a portion of a semiconductor device similar to the illustration of FIG. 3. However, in FIG. 4, particle 10' is much larger than particle 10 of FIG. 3. In this example, particle 10' is in contact with both conductors 6 and 8 at regions 12 and 14, respectively. If particle 10' is able to conduct electricity, the independent operation of conductors 6 and 8 will be jeopardized, creating cross-talk between conductors 6 and 8. If different devices are connected to conductors 6 and 8, a single particle 10' may destroy two devices embedded in the semiconductor wafer. Accordingly, particle 10' is what is commonly known as a "killer defect" since particle 10' may kill or prevent the normal operation of the semiconductor device which utilizes conductors 6 and 8. While the presence or absence of killer defects may be determined, this knowledge has not been utilized in any practical method of analyzing the defect characteristics of a semiconductor wafer. In addition, the presence or absence of killer defects has not been utilized in any practical method for in-line wafer defect disposition which involves the specific type of defect to be analyzed and the decision to scrap a wafer with too many defects.
FIGS. 5 and 6 are schematic illustrations of a portion of a semiconductor device for providing some additional background information regarding semiconductor defects. In FIG. 5, semiconductor device conductor lines 16 and 18 are separated by the distance 20. During the manufacturing process, particle 22 is introduced in the semiconductor wafer due to manufacturing defects or imperfections. Particle 22 has a diameter 24 and center point 26 as illustrated. In the situation illustrated in FIG. 5, particle 22 is in contact only with conductor 16 and is unable to extend to be in contact with both conductors 16 and 18. Therefore, particle 22 is considered to be a non-killer defect. Note that in this situation, the position of center 26 of particle 22, identified by dashed line 30, is spaced apart from center position 28 of conductors 16 and 18 by distance 32. As particle 22 moves closer toward conductor 18, the center 26 of particle 22 will also move closer to the center 28 of conductors 16 and 18. FIG. 6 illustrates this situation.
As shown in FIG. 6, the center 26 of particle 22 has moved closer to the center 28 of conductors 16 and 20. This is illustrated by the distance between center 28 and center line 30' being 32' which is smaller than the distance 32 in FIG. 5. Particle 22 is in contact with both conductors 16 and 20, and is therefore considered a killer defect. Thus, as the center 26 of particle 22 is moved closer to center 28 of conductors 16 and 20, the particle 22 will become more likely a killer defect. This, of course, presumes that particle 22 is large enough to be in simultaneous contact with both conductors 16 and 20.
FIG. 7 is a schematic illustration of a semiconductor wafer where several particles have been introduced therein. As shown in FIG. 7, each of the particles 38, 42, 46, 50 and 54 are all of the same size. In addition, particle 38 has a center 40, particle 42 has a center 44, particle 46 has a center 48, particle 50 has a center 52, and particle 54 has center 56. The particles 38, 42, 46, 50 and 54 are positioned across device conductors 34 and 36 in such a manner as to illustrate the sensitive area of a semiconductor device for a specific particle size.
The sensitive area is defined as the area between two independent conductors which contains the center point of a killer defect particle. That is, when the center of a particle of sufficient diameter is located in the sensitive area, the particle will be a killer defect. Thus, particles 42, 46 and 50 are all killer defect particles, and therefore, define the width of sensitive area 58. Since particles 38 and 54 are not killer defect particles, the sensitive area boundaries are located between center 40 of particle 38 and center 44 of particle 42, and also between center 52 of particle 50 and center 56 of particle 54. The height of sensitive area 58 is defined by the height of conductors 34 and 36. Accordingly, FIG. 7 illustrates a sensitive area 58 for a given particle size, indicating that when the center of the particle is within the sensitive area, the particle will be a killer defect.
FIG. 8 is a schematic diagram of a semiconductor wafer illustrating different sensitive areas for different particle sizes. Particles 64 and 66 are of equal size. In addition, particles 70 and 72 are of the same size, but smaller than particles 64 and 66. All particles 64, 66, 70 and 72 are defect killer particles since all of the particles are in contact with both device conductors 60 and 62 causing device failure. For the larger particles 64 and 66, the width of the sensitive area is defined by distance 68 between the centers of the these particles. Similarly, for the smaller particles 70 and 72, the sensitive area width is defined by the distance 74 between centers of particles 70 and 72. As is clearly illustrated in FIG. 8, the smaller the particle size, the smaller the sensitive area width, and conversely, the larger the particle size the larger the sensitive area width. The sensitive area width will reach a maximum threshold and saturate when half the width of the particle is greater than the distance between conductors 60 and 62.
FIG. 9 is a graphical illustration of the defect sensitive area D(R) as a function of the particle size R. As shown in FIG. 9, the initial particle size Ro reflects the smallest particle size which can be considered a killer defect, i.e., smallest particle size which will extend across and contact both conductors of semiconductor device. Curve 76 illustrates that as the particle size increases, the sensitive area will ultimately saturate and remain constant. While many have recognized these dynamics of the sensitive area in relation to the particle size, this information has not been used in such a manner which assists in the determination of whether a particular semiconductor wafer requires inspection and analysis, particularly in manufacturing environments where such decisions must be made quickly and efficiently. In addition, the sensitive area has also not been used in connection with in-line defect disposition.
FIGS. 10 and 11 are schematic diagrams of portions of different semiconductor wafers showing different sensitive areas. As illustrated in FIG. 10, semiconductor wafer 78 includes a sensitive area 82 in semiconductor device 80, and includes sensitive area 86 in semiconductor device 84. FIG. 11 shows that semiconductor wafer 88 includes sensitive area 92 in semiconductor device 90, and includes a sensitive area 96 in semiconductor device 94. As can be seen in FIGS. 10 and 11, semiconductor wafer 78 has a larger combined sensitive area 82 and 86 than the combined sensitive areas 92 and 94 of semiconductor wafer 88. As described previously, a larger sensitive area will permit larger particles to be introduced into the semiconductor device without causing failures. Accordingly, one method of determining whether the semiconductor wafer should be inspected and analyzed would be to select the semiconductor wafer of the smallest combined sensitive areas. The semiconductor wafer with the smallest combined sensitive areas would be more sensitive to smaller particles than would semiconductor wafers of larger combined sensitive areas. Therefore, semiconductor wafer 88 may be considered as being the wafer which needs to be closely scrutinized. However, this method does not consider whether the semiconductor is actually experiencing significant defects, and therefore, inspection of a semiconductor wafer with the smallest sensitive areas may not necessarily dramatically increase device yield. In addition, this method considers only the combined sensitive area and does not consider the relative size of the individual sensitive areas.
Another item of information which may be collected regarding the characteristics of the semiconductor wafer relates to what is called the "wafer index." To understand the wafer index, the relationship between defect count and particle size is described. FIG. 12 is a diagram illustrating the relationship between particle size and defect count. A semiconductor wafer having small particles will tend to have a higher defect count as shown at 100, than a semiconductor wafer which experiences particles of larger size for the same area of the semiconductor wafer which is shown at 102. The overall curve 98, therefore, illustrates the basic relationship that, as particle size increases, the defect counts for the number of particles which are introduced into the semiconductor wafer will decrease. Accordingly, the defect count is inversely proportional to the size of particle size, i.e., ##EQU1##
Curve 98 may be integrated with respect to particle size and sensitive area as shown in FIG. 13. FIG. 13 illustrates as 104 the integration of curve 98 of FIG. 12 with respect to particle size. Area 106 represents the defect sensitive area index for the wafer, where the ##EQU2## The higher the defect sensitive area index for the wafer, the more sensitive the semiconductor is to defects. Accordingly, the semiconductor wafer having a high defect sensitive area index may be selected for inspection and analysis. However, simply because one semiconductor wafer has a higher index than another does not necessarily provide detailed defect information that may be compared between wafers.
We have discovered, however, that the above methods of analyzing a semiconductor wafer to determine whether a wafer should be inspected and analyzed are deficient for several reasons. For example, simply counting the number of particles on the semiconductor wafer is no indication of whether these particles have actually caused device or circuit failure or the amount circuit failures experienced, as many of these particles may be non-killer defects. In this situation, the semiconductor circuits will still function in accordance with their original design. Thus, these in-line particle counts tend to overestimate the yield loss of devices in a semiconductor wafer, and unnecessary inspection and analysis is wasted on semiconductor wafers not experiencing serious problems.
We have further discovered since different semiconductor wafers have different integrated masking layouts, the defect sensitive area layouts will vary from wafer to wafer. Further, simply using the defect sensitive areas as an indication of which semiconductor wafer needs to be inspected may not be an appropriate gauge to compare a mature semiconductor product with a new product. For example, a mature product may already have undergone a significant amount of evaluation and optimization, and therefore, the mature product should perhaps be examined based on criteria other than simply the sensitive area criteria which ignores the product characteristics.
We have also discovered that determining which semiconductor requires defect reduction cannot be based merely on the highest number of in-line particle counts. As described above, even though a semiconductor wafer has many particle counts, these particle counts may not necessarily be killer defects which require immediate attention. Therefore, prioritizing the semiconductor wafers based on the highest number of particle counts may be inappropriate.
Finally, we have discovered that merely combining or adding all of the sensitive areas of the entire semiconductor wafer as another approach for determining whether the semiconductor wafer should be inspected and analyzed is also inefficient. This method does not take into account whether these defect sensitive areas are in fact experiencing defects. Thus, the semiconductor wafer with the most defect sensitive areas may not necessarily be the semiconductor wafer which is experiencing the most failures. For example, consider the situation where a semiconductor wafer has many defect sensitive areas which are much larger than the defect sensitive areas of another semiconductor wafer. The second semiconductor wafer with the smaller sensitive areas may experience more failures since in this case the smaller particle counts are the more likely to be killer defects.
Accordingly, it is desirable to determine not only the semiconductor wafer which is likely to experience more defects than other semiconductor wafers, but also the semiconductor wafer which is most likely to experience the greatest number of device defects.
It is further desirable to be able to determine not only the semiconductor wafer which is most likely to experience device losses, but also the specific layer of the semiconductor wafer which is likely to have the highest number of device losses. It is further desirable to determine the specific layers of the semiconductor wafer which are most likely to experience device losses in an automated and efficient manner to facilitate use of this information in a real-time manufacturing process.
It is also desirable to obtain the above information relating to device defects associated with a specific layer as well as the semiconductor wafer as a whole for various particle sizes.
It is further desirable to integrate in an efficient manner the information which is typically collected from the various wafer inspection tools. For example, it is desirable to integrate the particle count information which is generally determined using one inspection machine with sensitive area information which is generally collected using a second inspection machine.